(1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more particularly, to a method to eliminate shorts between adjacent conducting lines due to interlevel dielectric voids, known as keyholes, in the manufacture of integrated circuits.
(2) Description of the Prior Art
Feature size reduction is essential for realizing increased device content and higher switching speeds on integrated circuits. Inter-electrode spacings of 0.2 microns are now in fabrication. As these spacings are reduced, and the conductor height to spacing ratio approaches 4:1, it is difficult to deposit dielectric material over these electrodes without creating gaps or voids in the dielectric material.
In FIG. 1, a cross-section of two conducting lines 44 patterned on substrate 40 in an integrated circuit is shown. A layer of dielectric 46 comprised of silicon oxide overlays the conducting lines and the surface of the substrate 40.
A problem typical to the art is shown in FIG. 1. The conducting lines 44 have a spacing S1 of about 0.2 microns or less. The aspect ratio of height to width of the gap between the conducting lines is currently about 2:1, but is becoming higher. At this close spacing, air gaps, voids, or keyholes 42 will form in the dielectric oxide layer 46 in the area between the conducting lines 44. These air gaps can be either helpful or harmful to the integrated circuit depending on subsequent processing. Air gaps in the dielectric can be helpful because the dielectric constant of air is much less than that of silicon oxide. The capacitive coupling between the two transistors can be reduced by the air gap. This improves circuit performance. These voids can cause real problems, however, in situations where the compromised integrity of the dielectric can allow a shorting condition to occur. For example, when contacts are made through openings in the dielectric, the presence of a keyhole could cause two contacts to be connected through the keyhole causing a short. In a dynamic random access memory (DRAM) integrated circuit, for example, two cells could be connected through a keyhole, causing a twin-bit failure.
FIG. 2 demonstrates the same problem where silicon nitride spacers 48 are deposited along the conducting line 44 sidewall. Here, because of the presence of the spacers 48, the aspect ratio is higher than 2:1. Subsequent deposition of the dielectric oxide layer 46 will again result in the formation of a keyhole 42.
Several prior art approaches attempt to address the problems of voids in the dielectric layer. U.S. Pat. No. 5,665,657 to Lee teaches a method to remove voids in spin on glass layers by using an etch and fill method. U.S. Pat. No. 5,858,870 to Zheng et al teaches a method to fill gaps and planarize the dielectric layer using an anti-reflective coating with a chemical-mechanical polishing (CMP) etch stop. U.S. Pat. No. 5,817,567 to Jang et al teaches a method of shallow trench isolation (STI) where a layer of hard dielectric material is placed over a conformal silicon oxide. This is then planarized using CMP. U.S. Pat. No. 5,728,621 to Zheng et al teaches a method of STI planarization using a combination of high-density plasma (HDP) oxide and spin-on-glass (SOG) layers. U.S. Pat. No. 5,721,173 to Yano et al teaches a method of STI using selective etching of dielectric films. U.S. Pat. No. 5,679,606 to Wang et al teaches a method where interlevel dielectric structures are formed using an in-situ multi-step electron cyclotron resonance (ECR) oxide deposition process.